Memory tests are devised to uncover faults with storage cells and the access to these storage cells arising in part from improper design, lack of design margins or processing deficiencies. Generally, these tests are designed to be extensive and exhaustive to ensure that no bit defects, either hard defects or intermittent failures find their way into the field.
Semiconductor memories can, for example, be characterized as volatile random access memories (RAMs) or nonvolatile read only memories (ROMs), where RAMs can either be static (SRAM) or dynamic (DRAM) differing mainly in the manner by which they store a state of a bit. In SRAM, for example, each memory cell includes transistor-based circuitry that implements a bistable latch, which relies on transistor gain and positive (e.g., reinforcing) feedback so that it can only assume one of two possible states, namely on (state 1) or off (state 2). The latch can only be programmed or induced to change from one state to the other through the application of a voltage or other external stimuli. This arrangement is desirable for a memory cell since a state written to the cell will be retained until the cell is reprogrammed.
SRAM is typically arranged as a matrix of thousands of individual memory cells fabricated in an integrated circuit chip, and address decoding in the chip allows access to each cell for read/write functions. SRAM memory cells use active feedback from cross-coupled inverters in the form of a latch to store or “latch” a bit of information. These SRAM memory cells are often arranged in rows and columns so that blocks of data such as words or bytes can be written or read simultaneously. Standard SRAM memory cells have many variations.
SRAM memory arrays come in all sizes from arrays having tens of cells, to arrays having billions of cells. SRAMs may also be provided as memory devices dedicated purely to memory storage operations, or as a memory array that is embedded within an integrated circuit (IC) that carries out one of a variety of other control and/or processing functions. Such embedded memory array applications may include, for example, an automotive engine controller or a communications IC, wherein the embedded SRAM memory array may store set-up parameters, coordinates, initial conditions, or other variables used by the IC. Accordingly, embedded SRAM memory array applications usually require smaller arrays than those dedicated purely to memory storage.
The basic CMOS SRAM cell generally includes two n-type or n-channel (nMOS) pull-down or drive transistors and two p-type (pMOS) pull-up or load transistors in a cross-coupled inverter configuration, which act as a bistable latch circuit, with two additional nMOS select or pass-gate transistors added to make up a six-transistor cell (a 6T cell). Additionally, application specific SRAM cells can include an even greater number of transistors. A plurality of transistors are utilized in SRAM requiring matched electrical characteristics to provide predictable cell switching characteristics, reliable circuit performance, and minimize array power dissipation. Accordingly, rapid and effective testing of SRAM cells and SRAM arrays becomes increasingly critical as current scaling trends continue in modern integrated circuits and embedded memory devices.
Static Noise Margin (SNM) is a key SRAM parameter that is a direct measure of how well an SRAM memory cell can maintain its state when it is perturbed by noise or with intrinsic imbalance between the cross coupled inverters and leakage defects within the transistors forming the SRAM bit. An SRAM bit can easily be upset when it is accessed if it is designed with insufficient SNM throughout its operating voltage range. An upset usually occurs when a cell is accessed. Accessed in this context, means that the word line for the bit is raised high for either reading from that bit or for writing to another bit on the same row of the memory array but on a different column of that memory array.
FIGS. 1A and 1B initially illustrate a conventional 6T SRAM cell 1, wherein some of these issues may be described.
FIG. 1A, for example, illustrates a schematic diagram for the conventional differential 6T static random access memory (SRAM) cell 1. SRAM cell 1 comprises a data storage cell, latch, or core cell 2, generally including a pair of cross-coupled inverters, for example, inverter 12 and inverter 14, the latch 2 operable to store a data bit state. As illustrated in FIG. 1A, the bit is stored in the latch 2 at the first and second latch nodes or data nodes N3 and N4, respectively, having a high or “0” state and a low or “1” state, respectively. Cell 1 also comprises a pair of wordline pass transistors 16, 18 to read and write the data bit between the cross-coupled inverters 12, 14 and bitlines BL 30, BL-bar 31, when enabled by wordline 32. FIG. 1B illustrates a simplified version of the cross coupled inverters 12 and 14 connected at data nodes N3 and N4.
Respective inverters 12, 14 comprise a p-type MOS (PMOS) pull-up or load transistors MP1 (20), MP2 (22) and an n-type (nMOS) pull-down or driver transistors MN1 (24), MN2 (26). Pass transistors MN3 (16), MN4 (18) are n-channel as well, which generally supply higher conductance than p-channel transistors. Pass transistors 16, 18 are enabled by wordline WL 32 and accessed by bitlines BL30, BLB 31 to set or reset the SRAM latch 1. FIG. 1A further illustrates that inverters 12, 14 of the SRAM memory cell 1 are connected together to a Vdd drain voltage line Vdd 40 and a Vss source voltage line Vss 50.
The differential 6T SRAM cell 1 comprises six transistors and is termed a 6T full CMOS SRAM cell. In general, SRAM cells are more stable and have better data retention where the respective pMOS (MP1 (20), MP2 (22)) and nMOS (24, 26) transistors are load balanced and matched for the two inverters (12, 14).
Functionally, the outputs of the two inverters provide opposite states of the latch, except during transitions from one state to another. The pass-gate transistors provide access to the cross-coupled inverters during a read operation (READ) or write operation (WRITE). The gate inputs of the pass transistors are typically connected in common to a word line (wordline or WL). The drain of one pass transistor is connected to a bit line (bitline or BL), while the drain of the other pass transistor is connected to the logical complement of the bit line (bitline-bar or BLB).
A WRITE to a 6T cell is enabled by asserting a desired value on the BL and then asserting the WL. Thus, the prior state of the cross-coupled inverters is overwritten with a current value. A READ is enabled by initially precharging both bitlines to a logical high state and then asserting the WL. In this case, the output of one of the inverters in the SRAM cell will pull one bitline lower than its precharged value. A sense amplifier detects the differential voltage on the bitlines to produce a logical “one” or “zero,” depending on the internally stored state of the SRAM cell.
However, as dimensions are continually reduced to scale down such devices, the time consumed in testing of memory cells can become a significant issue in the effective assessment of the cell, or the transistors of a cell, particularly in SRAM memory devices requiring matched transistor characteristics.
FIGS. 1A and 1B further illustrate some problematic aspects associated with the reading of an SRAM cell 1, for example, when node N3 has been stored with a “0” state. When the cell is read or accessed, the word line (WL 32) is turned on and the bit line (BL 30/BLB 31) is discharged from an initial pre-charged level at Vdd towards ground through the pass gate MN3 (16). The voltage at N3 rises as the discharge occurs as transistor MN3 (16) and MN1 (24) can be thought of a forming a potential divider. A well designed and well behaved cell would keep N3 as low as possible so that the action of the access on the state of the bit would not perturb any voltage on the bit prior to access in order to avoid upset of the bit state.
However, this desire for maximum stability needs to be balanced with the ability to write to the bit. The more stable a bit is, the more difficult it is to write to it. Conversely, the bit that is easily written to is inherently unstable. The objective of SRAM design is to optimize both read and write operations as much as possible as well as keeping to a small cell area, high read currents, and low standby current. When N3 exceeds the voltage threshold of driver transistor MN2 (26) of the back to back inverter 14, the bit “flips” and the data state is corrupted. In other words, the state of the bit in this example has changed from a zero to a one when the bit was accessed. This would result in a memory failure.
Often SRAM memory arrays are put into a lower power mode than standby. This is sometimes referred to as the data retention mode in which the array voltage supply is lowered to a voltage well below the minimum operating voltage specified for the memory. In this way, leakage currents from the memory cells can be further reduced for prolonged battery operation. If a bit is well balanced (left inverter characteristics is nearly the same as the right inverter), the minimum holding or retention voltage can be extremely low, on the order of about 0.2V. However, transistor imbalances and minor leakages will increase this retention voltage substantially to about 0.6V for 1.2V technologies. Hence, it is possible to have data corruption without accessing the memory but by simply going into the retention mode. The SNM of the bit 1 with its word line WL 32 shut off or disabled may be referred to as “standby SNM”, herein, and is another important parameter in SRAM design.
It follows, then, that knowing the distribution of SNM of SRAM bits in a memory product provides an accurate forecast of the number of single bit memory failures the product will experience that is related to cell disturb. Much effort is spent in the SRAM memory industry to gain accurate measures of SNM. A prior art industry standard method of obtaining SNM is to measure and plot what is commonly referred to as “Butterfly Curves”, as will be discussed and illustrated further in association with FIG. 1G, infra. Butterfly curves are typically obtained by carefully measuring the voltage transfer characteristics (VTC) on each side (left and right side or left and right inverter) of the SRAM bit configured as shown in FIG. 1A. The “butterfly” is formed by mirroring one side of the VTC with respect to a line passing through the origin at 45 degrees from the horizontal axis. The SNM is given by the length of the diagonal of the largest square that can be contained between the curves. If the two inverters (e.g., 12 and 14) are perfectly symmetrical, the squares on the upper and lower part of the curves will be identical. If asymmetry exists, then one will be larger than the other and the SNM is from the lesser of the two diagonals.
Thus, getting to an SNM value requires a relative large number of measurements and a relatively sophisticated algorithm to extract SNM numbers from VTCs. While it is relatively straightforward to measure VTCs at higher voltages, a long measuring time is required at low supply voltages to obtain accurate VTCs. This is because the external measurement probes have large input capacitances that require a considerable amount of time (e.g., milliseconds) to charge. Hence, lower supply measurements require much time per measurement and are usually prohibitive in a production test environment.
Accordingly, it would be desirable to obtain an on-chip parametric memory testing technique that provides an approximation to SNM without obtaining VTCs and the associated time consuming acquisition and post processing in order to provide massive data gathering for statistical analysis, particularly in an SRAM memory device.